As opposed to planar complementary metal-oxide-semiconductor (CMOS) devices, vertical field effect transistors (VFETs) are oriented with a vertical fin channel disposed on bottom source and drains and a top source and drain disposed on the vertical fin channel. A gate runs vertically alongside the vertical fin channel.
The process for forming a VFET begins with the patterning of fins in a substrate. Prior to forming the bottom source and drains using epitaxy, it is preferable to laterally trim down the fins below the vertical fin channels. That way, the bottom source and drain epitaxy will be closer to the vertical fin channels which can lead to a sharper junction as less aggressive thermal processing is needed for driving dopants into the extension region.
However, there are challenges in terms of mechanical stability after the lateral trimming. With a lot of trimming at its base, the fin can even fall over.
Therefore, techniques that permit lateral trimming at the base of the fin to be performed without compromising the mechanical stability of the fin would be desirable.